1. Technical Field
The present disclosure relates to a Manchester code receiving circuit, and more particularly to a technique for improving the jitter tolerance of a reception signal.
2. Related Art
A Manchester code is used in communication according to, for example, Fieldbus which is a standard for performing digital communication between measuring/controlling apparatuses. In a Manchester code, the signal level changes in the middle of a signal indicative of each 0/1 bit. Therefore, a reception clock signal which functions as the reference of the transmission can be transmitted while being superimposed on a data signal.
FIG. 7 is a block diagram showing a configuration example of a related-art data receiving circuit for receiving data which are encoded in a Manchester code. Referring to FIG. 7, a data receiving circuit 200 which receives data from a communication transmission path 100 includes a MAU (Medium Attachment Unit) 210, an edge detecting module 220, a reception clock extracting module 230, a code detecting module 240, and a reception controlling module 250. The transmission path 100 may be configured by wired means such as a coaxial cable, or by wireless means.
The MAU 210 converts an analog signal transmitted through the transmission medium of the communication transmission path 100, to a digitized reception signal. The edge detecting module 220 synchronizes the digitized reception signal to a clock signal inside the data receiving circuit 200, to produce a synchronized reception signal, detects rising and falling edges from the synchronized reception signal, and outputs an edge detection signal. The rate of the clock signal is 2N (N is an integer of three or more) times a predetermined communication rate.
FIG. 8 is a waveform chart showing a manner in which the edge detection signal is output from falling and rising edges of a synchronized reception signal of a Manchester code. The synchronized reception signal of a Manchester code changes at the middle of a bit time corresponding to the transfer time of one bit. When the change is detected, the edge detection signal having the clock width is output. In the case where the same bit signals are continuously output, for example, the edge detection signal is output also at the start of the latter bit time. Therefore, the edge detection signal indicates one of the boundaries and middle of a bit time.
Returning to the description of FIG. 7, the reception clock extracting module 230 produces a reception clock signal and a reception clock enable signal based on the clock signal and the edge detection signal. The reception clock signal is a clock signal for allowing the code detecting module 240 to sample a bit signal in which the signal level changes at the middle. Since one bit signal must be sampled two times, the rate of the reception clock signal is two times the communication rate per one bit.
The reception clock enable signal enables the reception clock signal every other time so that the reception controlling module 250 which is in the subsequent stage, and which receives the produced reception clock signal operates at a clock frequency corresponding to the communication rate that is one half of the rate of the reception clock signal.
The code detecting module 240 samples and decodes the synchronized reception signal at the rising timing of the reception clock signal to output a code type signal and received data. The code type signal indicates the preamble, the start delimiter, the end delimiter, the data code, etc. FIG. 9 shows the code definitions of the preamble, the start delimiter, and the end delimiter in a Manchester code, and an example of the data code (“11001010”).
Returning again to FIG. 7, the reception controlling module 250 controls the reception of the received data based on the received data and code type signal which are input to the module. This control operation is performed on the basis of the bit time. Therefore, the reception controlling module 250 uses the reception clock signal while the reception clock signal is enabled every other time by the reception clock enable signal.
The reception clock extracting module 230 includes a clock extraction counter 232 for producing the reception clock signal and the reception clock enable signal based on the clock signal and the edge detection signal. The clock extraction counter 232 counts the clock signal, and, when the rate of the clock signal is 2N times the predetermined communication rate, performs a wrap around operation of an N-bit width. When an overflow occurs, namely, the count value returns to 0. In the following description, the count value is indicated in hexadecimal notation. When N=4, for example, the count value changes in a sequence of 0, 1, 2, . . . , E, F, 0, 1, . . . in each clock cycle.
In the case of N=4, when the communication rate is the predetermined one, the bit time corresponds to 24=16 clock cycles. As shown in FIG. 10, therefore, the reception clock signal is inverted every 4 clock cycles, and the reception clock enable signal is inverted every 8 clock cycles. Namely, the reception clock signal is inverted when the count value of the clock extraction counter 232 changes to 4, 8, C, and 0, and the reception clock enable signal is inverted when the count value changes to 8 and 0.
When the bit width of the clock extraction counter 232 is N, the reception clock signal is inverted when the second significant bit of the clock extraction counter 232 changes, and the reception clock enable signal is inverted when the most significant bit changes.
In actual communication, however, bit time distortion occurs, and the bit time is lengthened or shortened with respect to 2N clock cycles of the clock signal. In this case, as shown in FIG. 11, the sampling interval which is set in accordance with the reception clock signal, and the bit time of the synchronized reception signal are misaligned with each other, and therefore the sampling of the synchronized reception signal sometimes fails. FIG. 11 shows an example where the bit time is longer than 2N clock cycles. In the broken line circle in the figure, the same signal is sampled two times.
In order to prevent such a situation from occurring, the reception clock extracting module 230 includes a clock extraction controlling module 231 which controls the count value based on the edge detection signal. In accordance with the count value of the clock extraction counter 232 at the timing when the edge detection signal is detected, the clock extraction controlling module 231 adjusts the next count value. Specifically, the count value is adjusted in the following manner. When the detected edge position leads an ideal edge position where there is no jitter (when the detection is done at an early timing), the count up operation is further advanced (+2) from the normal value (+1) by 1, and, when the detected edge position lags (when the detection is done at a late timing), the operation is further delayed (±0) from the normal value (+1) by 1.
When the value of the lower (N−1) bits of the clock extraction counter 232 at the timing when the edge detection signal is detected is from 1 to 2N-2, namely, the next count value is not increased and remains at the current count value, and, when the value of the lower (N−1) bits is from 2N-2+1 to 2N-1−1, the next count value is increased by 2 which is larger by 1 than normal one. In the former case, the same value is counted two times, and, in the latter case, the counting is skipped by 1. In the other case, the adjustment is not necessary, and therefore the count value is increased by an increment of 1 as usual.
In the case where the bit width of the clock extraction counter 232 is 4, when the communication rate is the predetermined one, the edge detection signal is detected at the timing when the count value is 0 or 8. In the case where the edge detection signal is detected at the timing when the count value is 0 or 8, therefore, the adjustment is not performed, and the count value is increased by 1 as usual.
In the case where the bit time is longer than the predetermined one, and the edge detection signal is detected at the timing when the count value is from 1 to 4 or from 9 to C, by contrast, the count value is not increased and remains at the current count value, and, in the case where the bit time is shorter than the predetermined one, and the edge detection signal is detected at the timing when the count value is from 5 to 7 or from D to F, the count value is increased by 2.
FIG. 12 is a timing chart illustrating an example of the operation of the circuit of FIG. 7. In the example, it is assumed that the bit time is longer than the predetermined one, and the edge detection signal is detected at timing T1 when the count value is 9. In this case, the next count value is not increased to A and remains at the current count value of 9 as indicated by the white numeral. Therefore, subsequent sampling timings can be delayed by one clock cycle of the clock signal. The reception clock extracting module 230 performs the above-described adjustment at respective timings T2, T3, T4, T5, and T6 to cause the count value to follow the distortion of the bit timing.
Patent Document 1 discloses a technique of a communication apparatus in a field bus system in which the consumption current of a field apparatus can be reduced, and which uses a Manchester code.
Patent Document 2 discloses a technique of a clock extracting circuit which can obtain correct position data with a constant period from a serial encoder.